Nonvolatile memories have progressed rapidly from read-only to electrically erasable programmable read-only memories or EEPROMs. Of these, great interest is currently being shown in the flash type, the cells of which are based on a stacked gate structure, and are programmed (written) by channel hot electron injection at the drain region, and erased by Fowler-Nordheim tunneling.
Flash memories, like other nonvolatile memories, may be variously organized according to a row and column cell arrangement wherein the cells in the same row are connected at the control gate terminal to the same word line, and the cells in the same column are connected at the drain terminal to the same bit line. In one known configuration, known as NOR architecture, the source terminals of at least part of the array are connected to a common source line, so that each bit line sees the cells connected to it in a parallel configuration, i.e., a NOR connection.
At present, flash memories are read/programmed byte by byte or word by word, and are erased globally (full chip erase) or partially by a particular portion of the overall array (sector erase). Although most present-generation flash-memory devices employ a dual-voltage power supply, typically V.sub.CC =5 V and V.sub.pp =12 V, several single-power-supply devices are available. Standard flash memories of the above types cannot operate with a supply voltage V.sub.CC of less than 5 V due to the high programming current required.
To reduce the programming current, new cell structures have been proposed which, as opposed to drain-side injection as in standard cells, provide for source-side injection (SSI) hot electron programming. These new cell structures have aroused considerable interest by permitting programming of the cells with a lower current as compared with that used to program standard cells, and by enhancing programming efficiency by approximately one order of magnitude.
One example of an SSI programming structure is described in U.S. Pat. No. 4,794,565, which issued on 27 Dec. 1988, and comprises asymmetrical drain and source regions. More specifically, a highly resistive region is provided close to the source region, so that its conductivity is not easily modulated by the control gate voltage; and programming is based on bringing the high lateral electric field in the silicon from the drain to the source where the vertical field in the oxide is highest.
Ideally, there should be no current flow between the drain and source regions during programming. In actual practice, however, this current is not eliminated entirely, but is considerably lower with respect to the standard structure.
Other structures have also been proposed to improve the above basic concept. One such cell is described, for example, in EP-A-O 530 644 filed on 25 Aug. 1992 (priority 30 Aug. 1991) by Texas Instruments, and in an article entitled "Buried Source-Side Injection (BSSI) for Flash EPROM Programming" by Cetin Kaya, David K. Y. Liu, Jim Paterson, Pradeep Shah, IEEE Electron Device Letters, Vol. 13, No. 9, September 1992, and is based on the presence of a low-doped region implanted deeply in the channel region, adjacent to the source region, and, therefore, beneath the floating gate region, but separated from the surface of the substrate.
BSSI or SSI cells are programmed by grounding the source terminal, and applying a high voltage (10-13 V) to the gate terminal and a lower voltage (3-3.5 V) to the drain terminal, so that the applied electric field produces electron flow from the low-doped region to the surface of the substrate. The electrons, accelerated by the high field value, travel through the gate oxide and are trapped in the floating gate region, thus writing the cell.
SSI or BSSI cells are erased by applying a high negative voltage (-10 V) to the control gate terminal and a low voltage (4-6 V) to the drain terminal (with a floating source terminal) to produce electron flow from the floating gate to the drain region. As such, programming and erasing are performed at different regions (source for programming, drain for erasing).
SSI or BSSI cells are read by inverting the drain and source terminal bias with respect to standard cells, to achieve a sufficient read current, and by applying a high voltage (supply voltage V.sub.CC of, say, 5 V) to the gate terminal, a low voltage (1-2 V) to the source terminal, and grounding the drain terminal.